1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly to programmable logic devices with embedded memory blocks.
2. Description of the Related Art
Programmable memory devices (PLDs) typically have one standard size of embedded memory block. When a block of memory greater than the standard size is desired, these standard sized memory blocks are chained together. However, this can decrease the speed with which the memory can be accessed. When a block of memory less than the standard size is desired, a portion of the standard sized memory block is unused, this is an inefficient use of silicon area.
In some PLDs, look-up-tables may be used as xe2x80x9cdistributed memory.xe2x80x9d In these PLDs, the logic elements of the PLD are used as memory rather than having distinct blocks of memory. One disadvantage to using logic elements as memory is that they can be slower than dedicated memory blocks. Additionally, the use of logic elements as memory reduces the logic capacity of the device.
The present invention relates to a programmable logic device (PLD) with memory blocks. In one embodiment, the PLD includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.